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JTAG-Booster for Analog Devices ADSP-21xxx
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as input.
L5ACK Inp // Link Port Acknowledge
L4ACK Inp // Link Port Acknowledge
L3ACK Inp // Link Port Acknowledge
L2ACK Inp // Link Port Acknowledge
L1ACK Inp // Link Port Acknowledge
L0ACK Inp // Link Port Acknowledge
BR1# Inp // Multiprocessing Bus Request
BR2# Inp // Multiprocessing Bus Request
BR3# Inp // Multiprocessing Bus Request
BR4# Inp // Multiprocessing Bus Request
BR5# Inp // Multiprocessing Bus Request
BR6# Inp // Multiprocessing Bus Request
ACK Inp // Memory Acknowledge
HBG# Inp // Host Bus Grant
RFS0 Inp // Receive Frame Sync
RCLK0 Inp // Receive Clock
TFS0 Inp // Transmit Frame Sync
TCLK0 Inp // Transmit Clock
RFS1 Inp // Receive Frame Sync
RCLK1 Inp // Receive Clock
TFS1 Inp // Transmit Frame Sync
TCLK1 Inp // Transmit Clock
BMS# Out,Hi // Boot Memory Select = CS# of Flash-EPROM
FLAG0 Out,Lo // Flag Pin = LEx
FLAG1 Out,Hi // Flag Pin = LEx
FLAG2 Out,Lo // Flag Pin = LEx
FLAG3 Out,Hi // Flag Pin = LEx
// The direction of each following pin can be set independent of the others,
// but this pins can not be read back.
REDY Inp // Host Bus Acknowledge
DT0 Out,Lo // Data Transmit
DT1 Out,Lo // Data Transmit
EMU# Inp // Emulation Status
// The following pin has an open drain output with a weak pull up.
// The pin is bidirectional.
CPA# Inp // Core Priority Access
// The following pins are output only pins.
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JTAG_ADSP-21xxxa.doc
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